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Rev 0; 3/08
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC
General Description
The DS4422 and DS4424 contain two or four I2C programmable current DACs that are each capable of sinking and sourcing current up to 200A. Each DAC output has 127 sink and 127 source settings that are programmed using the I2C interface. The current DAC outputs power up in a high-impedance state. Full-Scale Current 50A to 200A Full-Scale Range for Each DAC Determined by External Resistors 127 Settings Each for Sink and Source Modes I2C-Compatible Serial Interface Two Address Pins Allow Four Devices on Same I2C Bus Low Cost Small Package (14-Pin, 3mm x 3mm TDFN) -40C to +85C Temperature Range 2.7V to 5.5V Operating Range
Features
Two (DS4422) or Four (DS4424) Current DACs
DS4422/DS4424
Applications
Power-Supply Adjustment Power-Supply Margining Adjustable Current Sink or Source
Ordering Information
PART DS4422N+ DS4422N+T&R DS4424N+ DS4424N+T&R OUTPUTS 2 2 4 4 TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 14 TDFN 14 TDFN 14 TDFN 14 TDFN
Pin Configuration appears at end of data sheet.
+Denotes a lead-free package. T&R = Tape and reel.
Typical Operating Circuit
VCC VOUT0 VOUT1 RPU RPU SDA SCL A1 A0 GND VCC DC-DC CONVERTER OUT R0A FB R0B DC-DC CONVERTER FB R1B OUT R1A
DS4422/ DS4424
OUT0 OUT1
FS0 RFS0
FS1 RFS1
_______________________________________________________________ Maxim Integrated Products
1
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC DS4422/DS4424
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL Relative to Ground.............................................-0.5V to +6.0V Voltage Range on A0, A1, FS0, FS1, FS2, FS3, OUT0, OUT1, OUT2, and OUT3 Relative to Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature ...............................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL, A0, A1) Input Logic 0 (SDA, SCL, A0, A1) Full-Scale Resistor Values SYMBOL VCC VIH VIL RFS0, RFS1, (Note 2) RFS2, RFS3 (Note 1) CONDITIONS MIN 2.7 0.7 x VCC -0.3 40 TYP MAX 5.5 VCC + 0.3 0.3 x VCC 160 UNITS V V V k
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Supply Current Input Leakage (SDA, SCL) Output Leakage (SDA) Output Current Low (SDA) RFS Voltage I/O Capacitance SYMBOL ICC I IL IL I OL VRFS CI/O VOL = 0.4V VOL = 0.6V 3 6 0.976 10 VCC = 5.5V (Note 3) VCC = 5.5V CONDITIONS DS4422 DS4424 MIN TYP MAX 250 250 1 1 UNITS A A A mA V pF
OUTPUT CURRENT SOURCE CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output Voltage for Sinking Current Output Voltage for Sourcing Current Full-Scale Sink Output Current Output Current Full-Scale Accuracy Output Current Temperature Coefficient SYMBOL VOUT:SINK (Note 4) CONDITIONS MIN 0.5 0 50 -200 TYP MAX 3.5 VCC 0.75 200 -50 6 75 UNITS V V A A % ppm/C
VOUT:SOURCE (Note 4) IOUT:SINK (Notes 1, 4) +25C, VCC = 3.3V; using 0.1% RFS resistor (Note 2), VOUT0 = VOUT1 = 1.2V (Note 5)
Full-Scale Source Output Current IOUT:SOURCE (Notes 1, 4) I OUT:FS I OUT:TC
2
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC
OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output Current Variation Due to Power-Supply Change Output Current Variation Due to Output-Voltage Change Output Leakage Current at Zero Current Setting Output Current Differential Linearity Output Current Integral Linearity I ZERO DNL INL (Notes 6, 7) (Notes 7, 8) SYMBOL DC source DC sink DC source, V OUT measure at 1.2V DC sink, VOUT measure at 1.2V -1 -0.5 -1 CONDITIONS MIN TYP 0.32 0.42 0.16 0.16 +1 +0.5 +1 MAX UNITS %/V %/V A LSB LSB
DS4422/DS4424
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading SYMBOL f SCL tBUF tHD:STA tLOW tHIGH tDH:DAT t SU:DAT t SU:STA tR tF t SU:STO CB (Note 10) (Note 10) (Note 10) (Note 9) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF
Note 1: Note 2: Note 3:
All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Input resistors (RFS) must be between the speciifed values to ensure the device meets its accuracy and linearity specifications. Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS). Note 4: The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications. Note 5: Temperature drift excludes drift caused by external resistor. Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. The expected incremental increase is the full-scale range divided by 127. Note 7: Guaranteed by design. Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. The expected value is a straight line between the zero and the full-scale values proportional to the setting. Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 10: CB--total capacitance of one bus line in pF.
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC DS4422/DS4424
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS4422/4 toc01
SUPPLY CURRENT vs. TEMPERATURE
DS4422/4 toc02
VOLTCO (SOURCE)
40k LOAD ON FS0, FS1, FS2, AND FS3 -175 IOUT (A)
DS4422/4 toc03
250
250 VCC = 5.0V 200 SUPPLY CURRENT (A)
-150
200 SUPPLY CURRENT (A)
150
150 VCC = 3.3V VCC = 2.7V 100 DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0, FS1, FS2, OR FS3
-200
100 DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0, FS1, FS2, OR FS3
-225
50
50
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-250 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOUT (V)
VOLTCO (SINK)
DS4422/4 toc04
TEMPERATURE COEFFICIENT vs. SETTING (SOURCE)
DS4422/4 toc05
TEMPERATURE COEFFICIENT vs. SETTING (SINK)
TEMPERATURE COEFFICIENT (C/ppm) +25C TO -40C 0 -50 -100 -150 -200 -250
DS4422/4 toc06
250 40k LOAD ON FS0, FS1, FS2, AND FS3 225 IOUT (A)
200 TEMPERATURE COEFFICIENT (C/ppm) 150 100 50 0 -50 -100 FOR THE 50A TO 200A CURRENT SOURCE RANGE
50
+25C TO -40C
+25C TO +85C
200
175
+25C TO +85C
150 0 0.5 1.0 1.5 2.0 VOUT (V) 2.5 3.0 3.5 4.0
FOR THE 50A TO 200A CURRENT SINK RANGE 0 25 50 75 100 125
0
25
50
75
100
125
SETTING (DEC)
SETTING (DEC)
INTEGRAL LINEARITY
DS4422/4 toc07
DIFFERENTIAL LINEARITY
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE
DS4422/4 toc08
1.00 0.75 0.50 INL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 25 50 75 100 FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE
1.0
125
0
25
50
75
100
125
SETTING (DEC)
SETTING (DEC)
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC
Pin Description
PIN DS4424 1 2 3 4 5 6 7 8 10 12 14 9, 11 13 -- -- DS4422 1 2 3 -- -- 6 7 8 10 -- -- 9, 11 13 4, 5, 12, 14 -- NAME SDA SCL GND FS3 FS2 FS1 FS0 OUT0 OUT1 OUT2 OUT3 A0, A1 VCC N.C. EP Address Select Inputs. Determines the I2C slave address by connecting VCC or GND. See the Detailed Description section for the available device addresses. Power Supply No Connection Exposed Pad. Leave floating or connect to GND. Current Output. Sinks or sources the current determined by the I2C interface and the resistance connected to FSx. (The DS4422 has only two outputs: OUT0 and OUT1.) Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (The DS4422 has only two inputs: FS0 and FS1.) FUNCTION I2C Serial Data. Input/output for I2C data. I2C Serial Clock. Input for I2C clock. Ground
DS4422/DS4424
Block Diagram
SDA SCL A1 A0
VCC
I2C-COMPATIBLE SERIAL INTERFACE
DS4422/DS4424
VCC F8h SOURCE OR SINK MODE GND CURRENT DAC0 F9h 127 POSITIONS EACH FOR SINK AND SOURCE MODE FAh FBh
CURRENT DAC1
CURRENT DAC2
CURRENT DAC3
FS0 RFS0 OUT0
FS1 RFS1 OUT1
FS2 RFS2 OUT2
FS3 RFS3 OUT3
DS4424 ONLY
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC DS4422/DS4424
Detailed Description
The DS4422/DS4424 contain two or four I2C adjustable current sources that are each capable of sinking and sourcing current. Each output (OUT0, OUT1, OUT2, and OUT3) has 127 sink and 127 source settings that can be controlled by the I2C interface. The full-scale ranges and corresponding step sizes of the outputs are determined by external resistors, connected to pins FS0, FS1, FS2, and FS3, that can adjust the output current over a 4:1 range. Pins OUT2, OUT3, FS2, and FS3 are only available on the DS4424. The formula to determine RFS (connected to the FSx pins) to attain the desired full-scale current range is: Equation 1: V RFS = RFS x 127 16 x IFS Where IFS is the desired full-scale current value, VRFS is the RFS voltage (see the DC Electrical Characteristics table), and RFS is the external resistor value. To calculate the output current value (IOUT) based on the corresponding DAC value (see Table 1 for corresponding memory addresses), use equation 2. Equation 2: IOUT = DAC Value(dec) x IFS 127
I2C Slave Address The DS4422/DS4424 respond to one of four I2C slave addresses determined by the two address inputs, A0 and A1. The address inputs should be connected to either VCC or ground. Table 1 lists the slave addresses determined by the address input combinations.
Table 1. Slave Addresses
A1 GND GND VCC VCC A0 GND VCC GND VCC SLAVE ADDRESS (HEX) 20h 60h A0h E0h
Memory Organization
To control the DS4422/DS4424's current sources, write to the memory addresses listed in Table 2.
Table 2. Memory Addresses
MEMORY ADDRESS (HEX) F8h F9h FAh* FBh* CURRENT SOURCE OUT0 OUT1 OUT2* OUT3*
On power-up the DS4422/DS4424 output zero current. This is done to prevent them from sinking or sourcing an incorrect amount of current before the system host controller has had a chance to modify the device's setting. As a source for biasing instrumentation or other circuits, the DS4422/DS4424 provide a simple and inexpensive current source with an I2C interface for control. The adjustable full-scale range allows the application to get the most out of its 7-bit sink or source resolution. When used in adjustable power-supply applications (see Typical Operating Circuit), the DS4422/DS4424 do not affect the initial power-up voltage of the supply because they default to providing zero output current on power-up. As the devices source or sink current into the feedback-voltage node, they change the amount of output voltage required by the regulator to reach its steadystate operating point. Using the external resistor, RFS, to set the output current range, the DS4422/DS4424 provide some flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined.
*Only for DS4424.
The format of each output control register is given by:
MSB S D6 D5 D4 D3 D2 D1 LSB D0
Where:
BIT NAME Sign Bit FUNCTION Determines if DAC sources or sinks current. For sink S = 0; for source S = 1. 7-Bit Data Controlling DAC Output. Setting 0000000b outputs zero current regardless of the state of the sign bit. POWER-ON DEFAULT 0b
S
DX
Data
0000000b
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC
Example: RFS0 = 80k and register 0xF8h is written to a value of 0xAAh. Calculate the output current. IFS = (0.976V/80k) x (127/16) = 96.838A The MSB of the output register is 1, so the output is sourcing the value corresponding to position 2Ah (42 decimal). The magnitude of the output current is equal to: 96.838A x (42/127) = 32.025A STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 1 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup and hold time requirements (Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a
DS4422/DS4424
I2C Serial Interface Description
I2C Definitions The following terminology is commonly used to describe I2C data transfers: I 2 C Slave Address: The slave address of the DS4422/DS4424 is determined by the state of the A0 and A1 pins (see Table 1). Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 1 for applicable timing.
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 1. I2C Timing Diagram
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC DS4422/DS4424
TYPICAL I2C WRITE TRANSACTION MSB START A1 A0 1 0 0 0 0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER/MEMORY ADDRESS *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED) 20h A) SINGLE BYTE WRITE -WRITE REGISTER F9h TO 00h B) SINGLE BYTE READ -READ REGISTER F8h F9h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK 21h REPEATED START 0 0 1 0 0 0 0 1 SLAVE ACK STOP
START 0 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK 20h F8h
DATA MASTER NACK STOP
START 0 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK
Figure 2. I2C Communication Examples
NACK by transmitting a one during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 2). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4422/DS4424 slave address is determined by the
state of the A0 and A1 address pins. Table 1 describes the addresses corresponding to the state of A0 and A1. When the R/W bit is 0 (such as in A0h), the master is indicating that it will write data to the slave. If R/W = 1 (A1h in this case), the master is indicating that it wants to read from the slave. If an incorrect slave address is written, the DS4422/DS4424 assume the master is communicating with another I 2 C device and ignore the communication until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
I2C Communication Writing to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition.
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC DS4422/DS4424
VCC VOUT* = 2.0V 4.7k 4.7k SDA SCL A1 A0 GND VCC DC-DC CONVERTER OUT I0A FB I0B R0B= 2.67k R0A = 4.00k VFB* = 0.8V
DS4422/ DS4424
OUT0
FS0 RFS0 = 80k IOUT0
*VOUT AND VFB VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH VOUT AND VRFS OF THE DS4422/DS4424.
Figure 3. Example Application Circuit
Applications Information
Example Calculations for an Adjustable Power Supply
In this example, the Typical Operating Circuit is used as a base to create Figure 3, a DC-DC output voltage of 2.0V with 20% margin. The adjustable power supply has a DC-DC converter output voltage, VOUT, of 2.0V and a DC-DC converter feedback voltage, VFB, of 0.8V. To determine the relationship of R0A and R0B, start with the equation: VFB = R0B x VOUT R0A + R0B
And: V - VFB IR0A = OUT R0A To create a 20% margin in the supply voltage, the value of VOUT is set to 2.4V. With these values in place, R0B is calculated to be 2.67k, and R0A is calculated to be 4.00k. The current DAC in this configuration allows the output voltage to be moved linearly from 1.6V to 2.4V using 127 settings. This corresponds to a resolution of 6.3mV/step.
Substituting VFB = 0.8V and VOUT = 2.0V, the relationship between R0A and R0B is determined to be: R0A 1.5 x R0B IOUT0 is chosen to be 100A (midrange source/sink current for the DS4422/DS4424). Summing the currents into the feedback node produces the following: IOUT0 = IR0B - IR0A Where: V IR0B = FB R0B
VCC Decoupling To achieve the best results when using the DS4422/ DS4424, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surfacemount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC DS4422/DS4424
Pin Configuration
TOP VIEW
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE T1433+2 DOCUMENT NO. 21-0137
SDA SCL GND FS3 (N.C.) FS2 (N.C.) FS1 FS0
1 2 3 4 5 6
14 13 12
OUT3 (N.C.) VCC OUT2 (N.C.) A1 OUT1 A0 OUT0
14 TDFN
+ DS4422/ DS4424
*EP
11 10 9 8
7
( ) INDICATES DS4422 ONLY. *EXPOSED PAD
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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